Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are design generation and integration, synthesis, placement, and routing of the system on the target device.
The use of pre-designed blocks of logic, known as intellectual property (IP) cores, have increased with current systems. IP cores may be used to implement various components on a target device, such as processors, interfaces, peripheral controllers, and dedicated components used for video and image processing, digital signal processing, and other functions. Some systems utilize dozens to hundreds of IP cores.
IP cores are typically offered as synthesizable register transfer level (RTL) description. RTL is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals between hardware registers, and the logical operations performed on those signals. RTL abstraction is used in hardware description languages such as Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and wiring can be derived.